Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies

The growing markets for low-power electronic devices energized by battery have created the need smaller power-efficient chips to prevent frequent charging of source. Nowadays market capitalization appliances is expected grow from USD 4.9 billion 2022 7.9 2027 as per global forecast published markets. main factor leading growth low power electronics includes demand energy saving components, miniaturization, and entry IoT (internet things) devices. In addition, increased investment automotive OEM (Original Equipment Manufacturer) governments promote adoption electric vehicles create more opportunities. this digital era, memory components play a major role in consumption incites research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology rapidly towards greater integration into single chip, resulting decrease chip sizes using less space. Speed stability also up. Combined density increases downtime continues. Stability reliability are an important issue static random access (SRAM) device. paper, design analysis based 9T SRAM cell variety technologies presented. focus review paper analyze test performance on several (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with help predictable (PTM) file. butterfly curve method used examine consistency bit terms noise margin (SNM). It clearly shown that it progresses 180nm 14nm delay decreases stability.